The following pages link to Rolf Drechsler (Q294812):
Displaying 23 items.
- (Q4677783) (← links)
- Minimization of Word-Level Decision Diagrams (Q4788457) (← links)
- Minimization of free BDDs (Q4788462) (← links)
- Verifying integrity of decision diagrams (Q4788463) (← links)
- Dynamic Re-Encoding During MDD Minimization (Q4804769) (← links)
- (Q4805283) (← links)
- (Q4825902) (← links)
- (Q4885887) (← links)
- (Q4885894) (← links)
- (Q4946957) (← links)
- On the relation between BDDs and FDDs (Q5096325) (← links)
- GenMul: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools (Q5157446) (← links)
- Finding Optimal Implementations of Non-native CNOT Gates Using SAT (Q5162614) (← links)
- (Q5389258) (← links)
- (Q5389328) (← links)
- (Q5444994) (← links)
- Correct Hardware Design and Verification Methods (Q5493242) (← links)
- Formal Methods for Hardware Verification (Q5899152) (← links)
- Clustering-Guided SMT($$\mathcal {L\!R\!A}$$) Learning (Q6487927) (← links)
- Is simulation the only alternative for effective verification of dynamic quantum circuits? (Q6637599) (← links)
- Artifacts for the FDL21 Paper: In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes (Q6700869) (← links)
- Artifacts for the 2022 ATVA Paper: SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification (Q6700876) (← links)
- Artifacts for the IEEE Internet of Things Journal Publication: Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT (Q6700878) (← links)
