Pages that link to "Item:Q1306169"
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The following pages link to Timing diagrams: Formalization and algorithmic verification (Q1306169):
Displaying 8 items.
- The Verus language: Representing time efficiently with BDDs (Q1589589) (← links)
- Formal verification of timed synchronous dataflow graphs using lustre (Q2043814) (← links)
- Reasoning about synchronization in GALS systems (Q2505629) (← links)
- (Q4028161) (← links)
- (Q4845010) (← links)
- Correct Hardware Design and Verification Methods (Q5493226) (← links)
- Correct Hardware Design and Verification Methods (Q5897067) (← links)
- Proving sequential function chart programs using timed automata (Q5958730) (← links)