Pages that link to "Item:Q1329086"
From MaRDI portal
The following pages link to An exercise in the automatic verification of asynchronous designs (Q1329086):
Displaying 6 items.
- On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP (Q1001805) (← links)
- Designing and using a single-step functional model of an asynchronous automaton (Q1057238) (← links)
- Hierarchical verification of asynchronous circuits using temporal logic (Q1070998) (← links)
- TTL: A modular language for hardware/software systems design. (Q1400574) (← links)
- Towards a unifying CSP approach to hierarchical verification of asynchronous hardware (Q2848424) (← links)
- (Q3346238) (← links)