Pages that link to "Item:Q1345656"
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The following pages link to Embedding hypercubes and related networks into mesh-connected processor arrays (Q1345656):
Displaying 12 items.
- New graph decompositions with applications to emulations (Q675853) (← links)
- On the reconfigurability of embedded loops on hypercubes and its application (Q1205514) (← links)
- Multiple graph embeddings into a processor array with spanning buses (Q1268780) (← links)
- Binary cube emulation of butterfly networks encoded by Gray code (Q1325980) (← links)
- Time and work optimal simulation of basic reconfigurable meshes on hypercubes (Q1878709) (← links)
- Work-preserving emulations of shuffle-exchange networks: An analysis of the complex plane diagram (Q1894348) (← links)
- An alternative mapping of 3-D space onto processor arrays (Q1970208) (← links)
- Hypercube emulation of interconnection networks topologies (Q2831031) (← links)
- The congestion of generalized cube communication pattern in linear array network (Q2929617) (← links)
- Optimum simulation of meshes by small hypercubes (Q3979258) (← links)
- Compressing cube-connected cycles and butterfly networks (Q4540063) (← links)
- An asymptotic relation between the wirelength of an embedding and the Wiener index (Q5051446) (← links)