Pages that link to "Item:Q2432214"
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The following pages link to Concurrent software verification with states, events, and deadlocks (Q2432214):
Displaying 11 items.
- A formal model for service-oriented interactions (Q436383) (← links)
- SAT-solving in CSP trace refinement (Q436423) (← links)
- Partial order reduction for state/event LTL with application to component-interaction automata (Q549692) (← links)
- Deadlock and starvation free reentrant readers-writers: a case study combining model checking with theorem proving (Q617922) (← links)
- Simulation for lattice-valued doubly labeled transition systems (Q2353987) (← links)
- Efficient verification of concurrent systems using local-analysis-based approximations and SAT solving (Q2418047) (← links)
- Using heuristic search for finding deadlocks in concurrent systems (Q2573636) (← links)
- Automated compositional abstraction refinement for concurrent C programs: a two-level approach (Q2845499) (← links)
- Partial Order Reduction for State/Event LTL (Q3605476) (← links)
- A Rewriting-Based Model Checker for the Linear Temporal Logic of Rewriting (Q5166636) (← links)
- Verification, Model Checking, and Abstract Interpretation (Q5711509) (← links)