Pages that link to "Item:Q2848424"
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The following pages link to Towards a unifying CSP approach to hierarchical verification of asynchronous hardware (Q2848424):
Displaying 3 items.
- Translating FSP into LOTOS and networks of automata (Q613134) (← links)
- On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP (Q1001805) (← links)
- Structure-based deadlock checking of asynchronous circuits (Q2637261) (← links)