Pages that link to "Item:Q305062"
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The following pages link to Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers (Q305062):
Displaying 5 items.
- Fast Radix-10 Multiplication Using Redundant BCD Codes (Q5268094) (← links)
- Low-Cost Binary128 Floating-Point FMA Unit Design with SIMD Support (Q5277616) (← links)
- Area-Efficient Multipliers Based on Multiple-Radix Representations (Q5280628) (← links)
- Improved Design of High-Performance Parallel Decimal Multipliers (Q5280770) (← links)
- Fast Bit-Parallel Binary Multipliers Based on Type-I Pentanomials (Q5375293) (← links)