Pages that link to "Item:Q421260"
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The following pages link to The complexity of VLSI power-delay optimization by interconnect resizing (Q421260):
Displaying 4 items.
- Optimal VLSI delay tuning by wire shielding (Q328471) (← links)
- The complexity of VLSI power-delay optimization by interconnect resizing (Q421260) (← links)
- Integrated circuit design. Power and timing modeling, optimization and simulation. 12th international workshop, PATMOS 2002, Seville, Spain, September 11--13, 2002. Proceedings. (Q1881180) (← links)
- On VLSI interconnect optimization and linear ordering problem (Q2443401) (← links)
