The following pages link to (Q4551149):
Displaying 10 items.
- Better abstractions for timed automata (Q342707) (← links)
- An exercise in the automatic verification of asynchronous designs (Q1329086) (← links)
- An abstraction algorithm for the verification of level-sensitive latch-based netlists (Q1425001) (← links)
- Verification of asynchronous circuits using timed automata (Q2842571) (← links)
- Modular synthesis of timed circuits using partial orders on LPNs (Q2842584) (← links)
- On Abstractions for Timing Analysis in the $\mathbb{K}$ Framework (Q3167528) (← links)
- Automatic Abstraction Refinement for Timed Automata (Q3510839) (← links)
- Abstraction Strategies for Computing Travelling or Looping Durations in Networks of Timed Automata (Q4603564) (← links)
- Tools and Algorithms for the Construction and Analysis of Systems (Q5308421) (← links)
- Static Analysis (Q5466559) (← links)
