Pages that link to "Item:Q5959326"
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The following pages link to VLSI circuit performance optimization by geometric programming (Q5959326):
Displaying 17 items.
- The complexity of VLSI power-delay optimization by interconnect resizing (Q421260) (← links)
- Approximation scheme for restricted discrete gate sizing targeting delay minimization (Q491218) (← links)
- Efficient preprocessing for VLSI optimization problems (Q967209) (← links)
- A tutorial on geometric programming (Q1027158) (← links)
- Multilevel optimization in VLSICAD (Q1412851) (← links)
- Posynomial parametric geometric programming with interval valued coefficient (Q1762404) (← links)
- A convex programming solution for gate-sizing with pipelining constraints (Q2147929) (← links)
- Transistor sizing of custom high-performance digital circuits with parametric yield considerations (Q2254194) (← links)
- Geometric programming with fuzzy parameters in engineering optimization (Q2379836) (← links)
- Posynomial geometric programming with interval exponents and coefficients (Q2462103) (← links)
- Posynomial geometric programming with parametric uncertainty (Q2569031) (← links)
- Performance optimization of VLSI interconnect layout (Q3122470) (← links)
- Solving a posynomial geometric programming problem with fully fuzzy approach (Q3388431) (← links)
- (Q3709898) (← links)
- Digital Circuit Optimization via Geometric Programming (Q5322147) (← links)
- Solving geometric programming problems with normal, linear and zigzag uncertainty distributions (Q5890837) (← links)
- Geometric programming problems with triangular and trapezoidal twofold uncertainty distributions (Q6151584) (← links)