The following pages link to Retiming synchronous circuitry (Q920937):
Displaying 30 items.
- Energy minimization with loop fusion and multi-functional-unit scheduling for multidimensional DSP (Q436738) (← links)
- Using fixed-point semantics to prove retiming lemmas (Q685101) (← links)
- Exact localisations of feedback sets (Q722200) (← links)
- Minimization of circuit registers: Retiming revisited (Q1003739) (← links)
- Decoupling the dimensions of a system of affine recurrence equations (Q1187518) (← links)
- Variables bounding based retiming algorithm. (Q1433961) (← links)
- An efficient algorithm for delay buffer minimization (Q1583703) (← links)
- Derivation of a rotator circuit with homogeneous interconnect (Q1607090) (← links)
- Timed Petri nets with reset for pipelined synchronous circuit design (Q2117152) (← links)
- A convex programming solution for gate-sizing with pipelining constraints (Q2147929) (← links)
- The resource-constrained modulo scheduling problem: an experimental study (Q2377171) (← links)
- Worst case analysis of decomposed software pipelining for cyclic unitary RCPSP with precedence delays (Q2434252) (← links)
- A polynomial-time algorithm for memory space reduction (Q2572378) (← links)
- Combining extended retiming and unfolding for rate-optimal graph transformation (Q2574208) (← links)
- Parallelizing synchronous data-flow graphs via retiming (Q2751882) (← links)
- Maximum weighted induced bipartite subgraphs and acyclic subgraphs of planar cubic graphs (Q2813347) (← links)
- A scheduling strategy for synchronous elastic designs (Q2895773) (← links)
- The Retiming Lemma: A simple proof and applications (Q3122481) (← links)
- Directed Graphs Without Short Cycles (Q3557536) (← links)
- Elasticity and Petri Nets (Q3599221) (← links)
- On the capabilities of systolic systems (Q4277374) (← links)
- Understanding retiming through maximum average-delay cycles (Q4277377) (← links)
- Retiming: Theory and practice (Q4397085) (← links)
- Approximating minimum feedback sets and multi-cuts in directed graphs (Q5101402) (← links)
- Tight Localizations of Feedback Sets (Q5102049) (← links)
- Large Feedback Arc Sets, High Minimum Degree Subgraphs, and Long Cycles in Eulerian Digraphs (Q5397736) (← links)
- Formal Methods in Computer-Aided Design (Q5492974) (← links)
- Tools and Algorithms for the Construction and Analysis of Systems (Q5703775) (← links)
- Extremal results on feedback arc sets in digraphs (Q6119220) (← links)
- Design and verification of pipelined circuits with timed Petri nets (Q6160969) (← links)
