Pages that link to "Item:Q2267084"
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The following pages link to Buffer planning for application-specific networks-on-chip design (Q2267084):
Displaying 6 items.
- An analytical model for Network-on-Chip with finite input buffer (Q352048) (← links)
- Real-time analysis of priority-preemptive NoCs with arbitrary buffer sizes and router delays (Q777069) (← links)
- A buffer minimization problem for the design of embedded systems (Q1767685) (← links)
- Variation-aware clock network buffer sizing using robust multi-objective optimization (Q2358032) (← links)
- Network flow based buffer planning (Q2778432) (← links)
- Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture (Q3628468) (← links)
