Pages that link to "Item:Q352048"
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The following pages link to An analytical model for Network-on-Chip with finite input buffer (Q352048):
Displaying 5 items.
- Real-time analysis of priority-preemptive NoCs with arbitrary buffer sizes and router delays (Q777069) (← links)
- Analysis of a tandem network model of a single-router network-on-chip (Q940931) (← links)
- A high level power model for network-on-chip (NoC) router (Q1040941) (← links)
- Buffer planning for application-specific networks-on-chip design (Q2267084) (← links)
- Analysis of the input to a buffer storage in front of a packet switch (Q4718652) (← links)