The following pages link to (Q3948585):
Displaying 18 items.
- Assume-admissible synthesis (Q520340) (← links)
- Proof systems for satisfiability in Hennessy-Milner logic with recursion (Q912592) (← links)
- Description and reasoning of VLSI circuit in temporal logic (Q1075756) (← links)
- The complementation problem for Büchi automata with applications to temporal logic (Q1088653) (← links)
- A decision procedure for combinations of propositional temporal logic and other specialized theories (Q1097264) (← links)
- The synthesis of communication protocols (Q1098296) (← links)
- Synthesis of communicating process skeletons from temporal-spatial logic specifications (Q1116944) (← links)
- Symbolic model checking: \(10^{20}\) states and beyond (Q1193587) (← links)
- Automated theorem proving in temporal logic: \(T\)-resolution (Q1322389) (← links)
- Relating word and tree automata (Q2576943) (← links)
- Introduction to Model Checking (Q3176359) (← links)
- Distributed Synthesis for Alternating-Time Logics (Q3510801) (← links)
- DESIGN AND SYNTHESIS OF SYNCHRONIZATION SKELETONS USING BRANCHING TIME TEMPORAL LOGIC (Q3512441) (← links)
- ATL* Satisfiability Is 2EXPTIME-Complete (Q3519515) (← links)
- A Hierarchical Completeness Proof for Propositional Interval Temporal Logic with Finite Time (Q3643267) (← links)
- On the Model Checking Problem for Some Extension of CTL* (Q5060078) (← links)
- (Q5136318) (← links)
- Axioms for real-time logics (Q5958467) (← links)
