Pages that link to "Item:Q5131170"
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The following pages link to An FPGA Implementation of Deep Spiking Neural Networks for Low-Power and Fast Classification (Q5131170):
Displaying 5 items.
- Analyzing and Accelerating the Bottlenecks of Training Deep SNNs With Backpropagation (Q3386449) (← links)
- Spatio-Temporal Optimization of Deep Neural Networks for Reconfigurable FPGA SoCs (Q3390133) (← links)
- Training Deep Convolutional Spiking Neural Networks With Spike Probabilistic Global Pooling (Q5083579) (← links)
- Efficient multi-scale representation of visual objects using a biologically plausible spike-latency code and winner-take-all inhibition (Q6054341) (← links)
- Method for Convolutional Neural Network Hardware Implementation Based on a Residue Number System (Q6486103) (← links)
