Pages that link to "Item:Q5932376"
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The following pages link to A low power approach to floating point adder design for DSP application (Q5932376):
Displaying 6 items.
- Reducing the mean latency of floating-point addition (Q1128723) (← links)
- Reducing switching activity of subtraction via variable truncation of the most-significant bits (Q1405462) (← links)
- Low-energy instruction precision assignment for multi-mode multiplier under accuracy and performance constraints (Q1707490) (← links)
- Lightweight floating-point arithmetic: Case study of inverse discrete cosine transform (Q1773575) (← links)
- A compact DSP core with static floating-point arithmetic (Q2432118) (← links)
- Energy-Efficient Floating-Point Unit Design (Q5280557) (← links)