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Figures of merit that characterize silicon gate-all-around nanowire FETs affected by line edge roughness variability - MaRDI portal

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Figures of merit that characterize silicon gate-all-around nanowire FETs affected by line edge roughness variability

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DOI10.5281/zenodo.7674909Zenodo7674909MaRDI QIDQ6703916

Dataset published at Zenodo repository.

Author name not available (Why is that?)

Publication date: 24 February 2023

Copyright license: No records found.



Description

Off-current, threshold voltage, sub-threshold slope and on-current values for two silicon gate-all-around nanowire FETs affected by line edge roughness (LER) variability, a 22 nm gate length device and a 10 nm gate length one. The LER profile that characterizes the roughness deformation is also included in the dataset. Different correlation length (CL) and root mean square (RMS) heights values are characterized.






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