Algorithms for parallel polygon rendering (Q1187667)
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scientific article; zbMATH DE number 43709
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Algorithms for parallel polygon rendering |
scientific article; zbMATH DE number 43709 |
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Algorithms for parallel polygon rendering (English)
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17 September 1992
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The booklet is devoted to the problem how to accelerate the graphic output for raster scan graphic systems. The author concentrates on rendering including HSE because of its time complexity causes a performance bottleneck in many of the current systems. The discussion of related works on design of parallel algorithms and architectures to support rendering is the starting point for developing noval algorithms and architectures respectively. The central idea is to use a SIMD processor array as a node in a MIMD architecture. The result is named Disputer, its programming can be done on the level of Occam. For the calculation of linear functions a noval algorithm is developed, it shows how using N-step coherence and parallelism in a general purpose parallel architecture can reach an efficient incremental rendering. Details are discussed for filling, HSE, texture, shading, anti-aliasing and others. A second algorithmic approach is based on precomputed surface patches. The emphasis lies on a N-step line generation algorithm using a parallel processor array. This precomputation gains extra speed by using additional storage space for patches. The dual paradigma parallel processor (Disputer) accomplishes the problem of significantly improving the performance of rendering operations in a SIMD array by off-loading the largest part of non-SIMD code to Transputers in the MIMD structure, different splitting methods are treated. The Transputers constructs compact descriptions of convex polygones in terms of surface patches which will be handled by the SIMD array. This can be done extremely efficiently when the surface patches are choosen as rendering primitives. A comparison of control parallel polygon clipping and data parallel clipping leads to a noval SIMD polygon clipping and gives the reader ideas for the wide scope of performance evaluation of different algorithms and architectures. The readers interest how further to improve performance by appropriate frame buffer organization remains open.
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rendering
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SIMD-architecture
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MIMD-architecture
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graphic output
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parallelism
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surface patches
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