Implementation of folding transformations on linear VSLI processor arrays (Q1195159)
From MaRDI portal
| This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use this page instead for the normal view: Implementation of folding transformations on linear VSLI processor arrays |
scientific article; zbMATH DE number 69181
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Implementation of folding transformations on linear VSLI processor arrays |
scientific article; zbMATH DE number 69181 |
Statements
Implementation of folding transformations on linear VSLI processor arrays (English)
0 references
7 October 1992
0 references
partitioned linear transformation
0 references
symmetric mapping
0 references
interlocking translation
0 references
data dependence
0 references
algorithm transformation
0 references
systolic array
0 references
folding transformation
0 references
processor array
0 references