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A parameterized ordering for cache-, register- and pipeline-efficient Givens QR decomposition - MaRDI portal

A parameterized ordering for cache-, register- and pipeline-efficient Givens QR decomposition (Q1284142)

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scientific article; zbMATH DE number 1271706
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English
A parameterized ordering for cache-, register- and pipeline-efficient Givens QR decomposition
scientific article; zbMATH DE number 1271706

    Statements

    A parameterized ordering for cache-, register- and pipeline-efficient Givens QR decomposition (English)
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    30 March 1999
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    A number of methods are known in the literature to calculate the QR decomposition of a matrix. The authors start with the basic Givens algorithm and construct a dependency graph such that any valid ordering through that graph yields an algorithm which is numerically identical to the original. Then they develop parametrized orderings through the graph, motivated by a simple model of a superscalar processor with a cache, registers, and a pipeline. The final algorithm simultaneously minimizes the number of loads and stores, while not stalling the floating point pipeline.
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    QR decomposition
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    Givens algorithm
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    graph
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    ordering
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    superscalar processor
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