A concurrent system for the computation of higher-order moments (Q1306186)

The authors present a fast concurrent systolic array system based on \(q+2\) layers of processing elements able to simultaneously compute second third and fourth moments (\(q\) the maximum lag to be handled by the system). It is shown that the computation time is of the order \(O(N+2q)\) and is faster than other solutions published in the literature (\(N\) is the data size). The processing elements are shown to be modular and thus suitable for VLSI implementation. A VLSI design in 1-\(\mu\)m CMOS architecture has been evaluted to 92,500 transistors for \(q=3\) and operators at 3.9 MHz with a total area of 3.56mm\(^2\) and 145mW dissipated power.