A multiprocessor architecture combining fine-grained and coarse-grained parallelism strategies (Q1323639)
From MaRDI portal
 | This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use this page instead for the normal view: A multiprocessor architecture combining fine-grained and coarse-grained parallelism strategies |
scientific article; zbMATH DE number 579975
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | A multiprocessor architecture combining fine-grained and coarse-grained parallelism strategies |
scientific article; zbMATH DE number 579975 |
Statements
A multiprocessor architecture combining fine-grained and coarse-grained parallelism strategies (English)
0 references
1 June 1994
0 references
coarse-grained parallelism
0 references
fine-grained parallelism
0 references
instruction-level parallelism
0 references
loop-level parallelism
0 references
performance comparisons
0 references
pipelining
0 references
multiprocessor
0 references
superscalar
0 references
