Gate elimination: circuit size lower bounds and \#SAT upper bounds (Q1704573)
From MaRDI portal
| This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use this page instead for the normal view: Gate elimination: circuit size lower bounds and \#SAT upper bounds |
scientific article; zbMATH DE number 6848999
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Gate elimination: circuit size lower bounds and \#SAT upper bounds |
scientific article; zbMATH DE number 6848999 |
Statements
Gate elimination: circuit size lower bounds and \#SAT upper bounds (English)
0 references
12 March 2018
0 references
circuit complexity
0 references
lower bounds
0 references
exponential time algorithms
0 references
satisfiability
0 references
0 references
0 references
0 references
0 references
0 references
0 references