Concurrency and hardware design. Advances in Petri nets (Q1868003)

The articles of this volume will be reviewed individually. Indexed articles: \textit{Benko, Igor; Ebergen, Jo}, Composing snippets, 1-33 [Zbl 1029.68003] \textit{Josephs, Mark B.; Furey, Dennis P.}, A programming approach to the design of asynchronous logic blocks, 34-60 [Zbl 1029.68506] \textit{Varshavsky, Victor; Marakhovsky, Vyacheslav}, GALA (globally asynchronous -- locally arbitrary) design, 61-107 [Zbl 1029.68508] \textit{Carmona, Josep; Cortadella, Jordi; Pastor, Enric}, Synthesis of reactive systems: Application to asynchronous circuit design, 108-151 [Zbl 1029.68505] \textit{Vogler, Walter; Wollowski, Ralf}, Decomposition in asynchronous circuit design, 152-190 [Zbl 1029.68006] \textit{LaRue, William; Solden, Sherry; Bhattacharya, Bishnupriya}, Functional and performance modeling of concurrency in VCC, 191-227 [Zbl 1029.68507] \textit{Balarin, Felice; Lavagno, Luciano; Passerone, Claudio; Sangiovanni-Vincentelli, Alberto; Sgroi, Marco; Watanabe, Yosinori}, Modeling and designing heterogeneous systems, 228-273 [Zbl 1029.68503] \textit{Møller, Jesper; Hulgaard, Henrik; Andersen, Henrik Reif}, Timed verification of asynchronous circuits, 274-312 [Zbl 1029.68005] \textit{Beerel, Peter A.; Xie, Aiguo}, Performance analysis of asynchronous circuits using Markov chains, 313-343 [Zbl 1029.68504]