The half-plane pull-in range of a second-order phase-locked loop (Q1916954)

The behaviour of an analog phase-locked loop (PLL), which is commonly used in instrumentation and communication systems, is governed by nonlinear differential equations. Being a frequency (phase) controlled (synchronised) system, the PLL is, among others, characterised by its pull-in range defined as the maximum value of frequency detuning \(\Delta \omega\) for which the phenomena of pull-in occurs. In this paper a definition is given for the PLL's half-plane pull-in range \(\Omega_2\). This definition implies that pull-in is guaranteed from anywhere in the phase plane's lower-half if \(0<\Delta \omega< \Omega_2\). It was shown that the PLL under consideration (second order type I) has an unstable separatrix cycle for \(\Delta \omega= \Omega_2\). A Galerkin-based algorithm was developed for computing the half-plane pull-in frequency. The algorithm determines the value \(\Delta \omega= \Omega_2\), at which the limit cycle bifurcates from the unstable separatrix cycle.