Performance evaluation of SNAIL: a multiprocessor based on the simple serial synchronized multistage interconnection network architecture (Q1960613)
From MaRDI portal
 | This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use this page instead for the normal view: Performance evaluation of SNAIL: a multiprocessor based on the simple serial synchronized multistage interconnection network architecture |
scientific article; zbMATH DE number 1387503
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Performance evaluation of SNAIL: a multiprocessor based on the simple serial synchronized multistage interconnection network architecture |
scientific article; zbMATH DE number 1387503 |
Statements
Performance evaluation of SNAIL: a multiprocessor based on the simple serial synchronized multistage interconnection network architecture (English)
0 references
12 January 2000
0 references
multistage interconnection networks
0 references
message combining
0 references
multiprocessors
0 references
VLSI implementation
0 references
empirical evaluations
0 references
