Hierarchical circuit comparison as a top-down VLSI design verification technique (Q2366261)
From MaRDI portal
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Hierarchical circuit comparison as a top-down VLSI design verification technique |
scientific article |
Statements
Hierarchical circuit comparison as a top-down VLSI design verification technique (English)
0 references
29 June 1993
0 references
