Virtual components design and reuse (Q2710194)

This book is a selection of papers giving a review of microelectronic virtual components design and their reuse from different points of view. The authors of 15 papers represent different positions -- research and academia, IP providers, EDA (Electronic Design Automation) vendors and industry. Virtual components also called IP (acronym from Intellectual Property system block) are going to be ready-to-use design specifications. They are subject to reuse in order to reduce costs and time-to-market.NEWLINENEWLINENEWLINESome classical topics in design reuse, like specification and generation of components, IP retrieval and cataloguing of interface customization, are revisited and discussed in depth. Moreover, newly emerged topics are presented -- such as IP quality, IP understandings, platform-based reuse, software IP, IP security, market analysis, and major initiatives like the MEDEA EDA roadmap.NEWLINENEWLINENEWLINEThe introductory paper outlines the current status of research and applications in virtual components fields as seen by important market player in this field. The market analysis has shown important factors and progress in this business. Next paper describes the roadmap for design automation (2nd release 2000) elaborated by MEDEA (Micro-Electronics Development for European Applications). It is a forecast how design automation of semiconductor manufacture could evolve in Europe, considering shortages in industrial development but also a tremendous reservoir of knowledge. Next, paper concerns methodology used by Cadence Design Systems to integrate practical SOC (System-On-Chip) platforms with abstract system design approach. Software services and resources such as CORBA , C++ as well as languages for documents such as XML are presented in next paper. Several papers describe essential apects of VHDL language. In order to assess the design quality, ARDID -- a VHDL quality analysis tool has been developed. It may test a variety of design features and lead to conclusions about quality through simulation of simplified models derived from VHDL descriptions. To understand better the legacy VHDL design coding, the VALET tool analyses program dependence graphs, signals and functions of digital blocks. The so called lambda-block analysis is suitable for inspecting the VHDL models to obtain a set of metrics, which is appropriate to estimate the complexity of design reuse. Another contribution to VHDL is an environment for automated generation of VHDL models, especially in the area of digital signal processors. Next paper considers mixed approach to models, which takes into account abstraction level simulation and behavioral synthesis. One paper is devoted to the cryptographic blocks for reuse library with special emphasis on virtual interface wrapper -- a flexible and generalized basis for different types of communication. The topic of virtual component interfaces is present in two papers. First paper is a presentation of interface specification framework based on the ideas from the Interface Behavioral Documentation Standard being elaborated by VSI Alliance (www.vsi.org).).The second one deals with interfaces of software modules used in design automation. Last main topic of the book is development and maintenance of IP repositories. A proposal of the IP retrieval task as case-based reasoning constraint satisfaction problem is described and the information about WWW repository attempting to integrate more CAD tools in the Web server is given.NEWLINENEWLINENEWLINEThe IP re-use is a hot topic in microelectronics design strongly supported by 2002 Workprogramme of European Union Framework (Action Line IV.1.8).