Substrate noise. Analysis and optimization for IC design (Q2716055)
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scientific article; zbMATH DE number 1601217
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Substrate noise. Analysis and optimization for IC design |
scientific article; zbMATH DE number 1601217 |
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30 May 2001
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integrated circuits
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circuit performance
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substrate noise
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noise transport characterization
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substrate extraction
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simulation
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optimization
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Substrate noise. Analysis and optimization for IC design (English)
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This monograph addresses the problem of modeling and characterization of interactions through the substrate and in particular, substrate noise. The work presents a summary of the state of the art in these areas. After an introductory chapter, chapter 2 describes mechanisms behind the generation and transport of substrate noise. In chapter 3, a review of techniques for noise transport characterization is given. Acceleration techniques for substrate extraction and simulation are presented in chapter 4. Substrate-aware computer-assisted design and optimization methods are reviewed in chapters 5 and 6. In chapter 7, the effects of substrate impedance on circuit and device performance is considered. Several studies are given to show the substrate as an insulator as well as a conductor of noise are presented in chapter 8. In addition, a number of guidelines for noise-aware design practices are included. There are four appendices and a reference list.
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0.7795917391777039
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0.7101531028747559
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