Test generation of the digital circuits based on the genetic algorithms (Q2720911)

A test generation algorithm for synchronous sequential circuits is developed. This algorithm is based on the genetic approach that is widely used for the solving of NP-completeness problems. As an individual is chosen a single test sequence consisting of test vectors. A union with fixed number of individuals is named the population. Over the best individuals in population are performed the crossing-over and mutation operations and than they form the new population. The quality of the individuals is a measure of the activity of the signals in the circuit in the presence of the specific fault and is the sum of the measure of all single test vectors. The calculation of the quality of individuals is based on the fault simulation. The proposed ``parallel by faults'' simulation method speeds up the process of the calculus of the individuals quality and therefore the test generation. The proposed algorithm is implemented in the C programming language and experimental results on the ISCAS-89 benchmark circuits are presented.