System-on-a-chip verification. Methodology and techniques (Q2734777)
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scientific article; zbMATH DE number 1637023
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | System-on-a-chip verification. Methodology and techniques |
scientific article; zbMATH DE number 1637023 |
Statements
23 August 2001
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verification
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System-on-a-chip verification. Methodology and techniques (English)
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Table of contents: Introduction; System-level verification; Block-level verification; Analog/mixed signal simulation; Simulation; Hardware/software co-verification; Static net-list verification; Physical verification and design sign-off.
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