Proceedings of the international workshop on discrete-event system design. DESDes '01, Przytok near Zielona Góra, Poland, June 27--29, 2001 (Q2743198)

The articles of this volume will be reviewed individually.NEWLINENEWLINEIndexed articles:NEWLINENEWLINE\textit{Zakrevskij, Arkadij}, Sequent model for representation of digital systems behavior, 3-10 [Zbl 1017.68064]NEWLINENEWLINE\textit{Tavares, Adriano; Couto, Carlos}, Estimation of WCET using a little language to describe microcontroller and DSP architectures, 11-16 [Zbl 0988.68642]NEWLINENEWLINE\textit{Soto, Enrique; Pereira, Miguel}, Implementing a Petri net specification in a FPGA using VHDL, 19-24 [Zbl 1017.68081]NEWLINENEWLINE\textit{Uzam, Murat; Avci, Mutlu; Yalçin, M. Kürşat}, Digital hardware implementation of Petri net based specifications: Direct translation from safe automation Petri nets to circuit elements, 25-33 [Zbl 1017.68082]NEWLINENEWLINE\textit{Karatkevich, Andrei}, On algorithms for decyclisation of oriented graphs, 35-40 [Zbl 0996.68123]NEWLINENEWLINE\textit{Erhard, Werner; Reinsch, Andreas; Schober, Torsten}, Modeling and verification of sequential control paths using Petri nets, 41-46 [Zbl 0996.68124]NEWLINENEWLINE\textit{Gomes, Luis; Barros, João Paulo}, Using hierarchical structuring mechanism with Petri nets for PLD based system design, 47-52 [Zbl 1019.68068]NEWLINENEWLINE\textit{Adamski, Marian}, A rigorous design methodology for reprogrammable logic controllers, 53-60 [Zbl 1018.68053]NEWLINENEWLINE\textit{Yamaguchi, Shin'nosuke; Wasaki, Katsumi; Shidama, Yasunari; Kawamoto, Pauline Naomi}, Automatic HDL generation for a DES codec for an encrypted NFS server based on extended Petri net, 61-66 [Zbl 1019.68069]NEWLINENEWLINE\textit{Miczulski, Piotr}, State space calculation algorithm of hierarchical Petri nets with application of decision diagrams, 67-72 [Zbl 1017.68083]NEWLINENEWLINE\textit{Andrzejewski, Grzegorz}, Timed Petri nets for software applications, 73-78 [Zbl 1017.68084]NEWLINENEWLINE\textit{Cheremisinov, Dmitrij I.}, Deriving programs from parallel algorithms of logical control, 79-84 [Zbl 1017.68158]NEWLINENEWLINE\textit{Pottosin, Yuri}, On optimal state-assignment of synchronous parallel automata, 85-90 [Zbl 1017.68065]NEWLINENEWLINE\textit{Lopes, Sérgio; Monteiro, João}, Simulation and targeting using OORT, 93-101 [Zbl 1017.68009]NEWLINENEWLINE\textit{Dvorak, Vaclav}, Optimizing SW/HW architecture for parallel embedded systems -- a case study, 103-108 [Zbl 0995.68595]NEWLINENEWLINE\textit{Szostak, Sławomir; Robak, Silvia; Stryjski, Roman; Franczyk, Bogdan}, UML extensions for modeling real-time and embedded systems, 109-114 [Zbl 1018.68013]NEWLINENEWLINE\textit{Hamuda, Grzegorz; Halang, Wolfgang}, Correctness proof of an operating system kernel for hard real time computing, 115-120 [Zbl 1019.68030]NEWLINENEWLINE\textit{Sadykhov, Raouf Kh.; Otwagin, Aliaksei V.}, Algorithm for optimization of parallel computations on the basis of genetic algorithms and model of a virtual network, 121-126 [Zbl 1019.68042]NEWLINENEWLINE\textit{Cheremisinova, Ljudmila}, State assignment of asynchronous parallel automata, 127-132 [Zbl 1018.68043]NEWLINENEWLINE\textit{Rawskii, Mariusz; Łuba, Tadeusz; Jachna, Zbigniew; Rzechowski, Rafał}, Functional decomposition -- the value and implication for modern digital designing, 135-140 [Zbl 0988.68647]NEWLINENEWLINE\textit{Kubátová, Hana}, Implementation of the FSM into FPGA, 141-146 [Zbl 1019.68014]NEWLINENEWLINE\textit{Chmiel, Mirosłav; Hrynkiewicz, Edward}, Remarks on parallel bit-byte CPU structures of progammable logic controllers, 147-152 [Zbl 0991.68683]NEWLINENEWLINE\textit{Hahanov, Vladimir I.; Babich, Anna V.; Mehedi, Masud M. D.}, System of digital device test generation for active HDL, 153-156 [Zbl 1018.68001]NEWLINENEWLINE\textit{Bandzerewicz, Mirosław; Sakowski, Wojciech; Wrona, Włodzimierz}, A systematic development of virtual components compatible to standard ICs. (An industrial experience), 157-162 [Zbl 0988.68640]NEWLINENEWLINE\textit{Caban, Dariusz}, A positional filter synthesis for FPGA implementation, 163-168 [Zbl 1019.68125]NEWLINENEWLINE\textit{Michalczak, Maciej; Skowroṅski, Zbigniew}, Implementation of pipelining mechanism in re-programmable logic structures with VHDL language usage, 169-174 [Zbl 1031.68512]NEWLINENEWLINE\textit{Jabłoński, Janusz}, Pipeline processing for serial realization of basical arithmetical operations, 175-180 [Zbl 0996.68003]NEWLINENEWLINE\textit{Bibilo, Pyotr; Kirienko, Natalia}, Bloch synthesis of combinational circuits in the basis of PLA and library gates, 181-186 [Zbl 0996.68868]NEWLINENEWLINE\textit{Hummel, Thorsten; Fengler, Wolfgang}, Design of embedded control systems using hybrid Petri nets, 189-194 [Zbl 1018.68054]NEWLINENEWLINE\textit{Idzikowska, Ewa}, Petri net models of VHDL control statements, 195-201 [Zbl 1019.68070]NEWLINENEWLINE\textit{Forczek, Miroslaw}, CHDL -- an approach for hardware design at the system level, 203-208 [Zbl 0996.68719]NEWLINENEWLINE\textit{Łabiak, Grzegorz}, Symbolic state exploration of controllers specified by means of statecharts, 209-214 [Zbl 1018.68055]NEWLINENEWLINE\textit{Wȩgrzyn, Agnieszka; Bubacz, Piotr}, XML application for modelling and simulation of concurrent controllers, 215-221 [Zbl 1019.68071]NEWLINENEWLINE\textit{Pereira, Miguel; Soto, Enrique}, Fail-safe VHDL descriptions of Petri net specifications, 223-228 [Zbl 1018.68056]NEWLINENEWLINE\textit{Wiśniewski, Remigiusz; Bukowiec, Arkadiusz; Wȩgrzyn, Marek}, Benefits of hardware accelerated simulation, 229-234 [Zbl 1018.68092]NEWLINENEWLINE\textit{Sadykhov, Raouf; Klimovich, Aliaksei; Podenok, Leonid}, Automatic system for TV raster parameters tuning, 237-242 [Zbl 0988.68641]NEWLINENEWLINE\textit{Przybylo, Jaromir; Gorgon, Marek}, Flexible resource arbiter for heterogeneous image processing system, 243-248 [Zbl 1002.68546]NEWLINENEWLINE\textit{Sadykhov, Raouf Kh.; Vatkin, Maksim E.}, Algorithm for image processing of integrated circuits on the basis of the ``neocognitron'' neural network, 249-254 [Zbl 1031.68634]NEWLINENEWLINE\textit{Prytkov, Valery A.; Sadykhov, Raouf Kh.}, Selection of close classes objects using brightness histogram, 255-258 [Zbl 0991.68684]NEWLINENEWLINE\textit{Vatkin, Maksim; Selinger, Mikhail}, The system of handwritten characters recognition on the basis of Legendre moments and neural network, 259-263 [Zbl 1018.68073]