VLSI synthesis of DSP kernels. Algorithmic and architectural transformations (Q2743245)

This book is devoted to describing the extremely fruitful ``marriage'' between digital signal processing (DSP) and integrated circuit technology. Specifically, the book presents algorithmic and architectural transformations with the aim of optimizing the weighted-sum based DSP kernels over the area-delay-power space. The considered transformations address implementation technologies that offer various degrees of programmability (thus flexibility) ranging from software programmable processors to customized hardwired solutions. After the introductory Chapter 1, Chapter 2 presents a comprehensive framework that encapsulates techniques for low power implementation of DSP algorithms on programmable DSP systems. These techniques are specialized for weighted-sum computations and for FIR (finite impulse response) filters. Chapter 3 exposes implementation using hardware multiplier(s) and adder(s), and evaluates the effectiveness of various data flow graph (DFG) transformations such as parallel processing, pipelining, re-timing and loop-unrolling with respect to weighted sum computation. Chapter 4 discusses various techniques for deriving multiple distributed arithmetic (DA) based structures that represent different data-points in the area-delay space. The problem of reducing power dissipation in the input data shift-register DA based FIR filters is also addressed.NEWLINENEWLINE Chapter 5 specifies a technique based on common subexpression precomputation for reducing the number of additions for non-adaptive signal processing applications in which the weight values are constant and known at design time. High-level synthesis of multi-precision DFGs is also examined. Chapter 6 focuses on optimized code generation of multiplication-free linear transforms, including directed acyclic graph (DAG) transformations to further improve performance and reduce power dissipation. Chapter 7 describes an implementation based on a residue number system (RNS) transformation, a high-speed parallel method to run addition, subtraction, and multiplication operations, used to compute weighted-sum and to reduce power-dissipation of DSP algorithms. To tie up all these techniques, Chapter 8 proposes a methodology to systematically identify transformations that exploit the characteristics of a given DSP algorithm and its implementation. Chapter 9 summarizes the key topics covered within this book to address VLSI synthesis and optimization of DSP (weighted-sum based) kernels.NEWLINENEWLINE The present book is a generous and most qualified offer to all developers, either researchers or managers interested in VLSI and DSP, but especially to practicing system designers involved in both hardware and software optimal implementation of DSP kernels.