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Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures - MaRDI portal

Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures (Q2985237)

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Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures
scientific article

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    title
    Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures (English)
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    author
    Seokin Hong
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    Soontae Kim
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    publication date
    16 May 2017
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    Identifiers

    zbMATH DE Number
    6715981
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