A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization (Q3139911)
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| Language | Label | Description | Also known as |
|---|---|---|---|
| English | A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization |
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A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization (English)
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30 January 1994
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CAD for VLSI
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design methodology
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hierarchical specification technique
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routing
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2-layer wiring
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layer assignment
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hierarchical physical synthesis
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