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Parallel multipliers with NOR gates based on G-minimum adders - MaRDI portal

Parallel multipliers with NOR gates based on G-minimum adders (Q3676064)

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scientific article
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English
Parallel multipliers with NOR gates based on G-minimum adders
scientific article

    Statements

    title
    Parallel multipliers with NOR gates based on G-minimum adders (English)
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    author
    Ging-Shung Yu
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    Saburo Muroga
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    publication date
    1984
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    zbMATH Keywords
    logic design
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    NOR gates
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    parallel multipliers
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    Identifiers

    DOI
    10.1007/BF00978712
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    zbMATH DE Number
    3896835
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