High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree (Q3680755)
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| Language | Label | Description | Also known as |
|---|---|---|---|
| English | High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree |
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High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree (English)
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1985
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arithmetic operations
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binary integer multiplication
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carry-propagation-free adder
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hardware algorithm
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high-speed multiplier
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redundant binary representation
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signed-digit number representation
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