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A BDD-based verification method for large synthesized circuits - MaRDI portal

A BDD-based verification method for large synthesized circuits (Q3840902)

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A BDD-based verification method for large synthesized circuits
scientific article

    Statements

    title
    A BDD-based verification method for large synthesized circuits (English)
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    author
    C. A. J. van Eijk
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    published in
    Integration
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    publication date
    13 August 1998
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    zbMATH Keywords
    formal verification
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    equivalence checking
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    binary decision diagrams
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    logic synthesis
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    structural similarity
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    Identifiers

    zbMATH DE Number
    1190108
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    Wikidata QID
    Q126297841
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