VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements (Q3840919)
From MaRDI portal
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements |
scientific article |
Statements
VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements (English)
0 references
13 August 1998
0 references
CELP
0 references
FS1016
0 references
speech coding
0 references
VLSI
0 references
low power
0 references
