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A Regular Layout for Parallel Adders - MaRDI portal

A Regular Layout for Parallel Adders (Q3934311)

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A Regular Layout for Parallel Adders
scientific article

    Statements

    title
    A Regular Layout for Parallel Adders (English)
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    author
    Richard P. Brent
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    H. T. Kung
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    publication date
    1982
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    zbMATH Keywords
    VLSI architecture
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    area-time complexity
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    carry lookahead
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    circuit design
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    combinational logic
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    models of computation
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    parallel addition
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    parallel polynomial evaluation
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    prefix computation
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    Identifiers

    zbMATH DE Number
    3750865
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    Wikidata QID
    Q55953421
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    OpenAlex ID
    W2168543008
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