Achieving optimality for gate matrix layout and PLA folding: a graph theoretic approach (Q4015507)
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| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Achieving optimality for gate matrix layout and PLA folding: a graph theoretic approach |
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Achieving optimality for gate matrix layout and PLA folding: a graph theoretic approach (English)
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13 January 1993
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combinatorial optimization
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gate matrix layout
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consecutive ones property
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VLSI design
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heuristic algorithms
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PLA folding
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matrix layout problem
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complexity
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