A methodology for hardware verification based on logic simulation (Q4302838)
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scientific article; zbMATH DE number 622318
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | A methodology for hardware verification based on logic simulation |
scientific article; zbMATH DE number 622318 |
Statements
A methodology for hardware verification based on logic simulation (English)
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30 March 1995
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hardware verification
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logic simulation
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ternary simulation
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circuit verification
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