A low latency architecture for computing multiplicative inverses and divisions in GF(2/sup m/) (Q4553217)
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scientific article; zbMATH DE number 1798153
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | A low latency architecture for computing multiplicative inverses and divisions in GF(2/sup m/) |
scientific article; zbMATH DE number 1798153 |
Statements
A low latency architecture for computing multiplicative inverses and divisions in GF(2/sup m/) (English)
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10 June 2003
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finite field division
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finite field inverse
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finite field multiplier
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VLSI architecture
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0.9076266
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0.90001386
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0.8963487
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0.88603604
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0.8857475
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0.8825421
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0.8785151
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