Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs (Q5268295)
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scientific article; zbMATH DE number 6733229
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs |
scientific article; zbMATH DE number 6733229 |
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Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs (English)
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20 June 2017
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0.83389145
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0.82883525
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