Figures of merit that characterize silicon gate-all-around nanowire FETs affected by line edge roughness variability (Q6703916)
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Dataset published at Zenodo repository.
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Figures of merit that characterize silicon gate-all-around nanowire FETs affected by line edge roughness variability |
Dataset published at Zenodo repository. |
Statements
Off-current, threshold voltage, sub-threshold slope and on-current values for two silicon gate-all-around nanowire FETs affected by line edge roughness (LER) variability, a 22 nm gate length device and a 10 nm gate length one. The LER profile that characterizes the roughness deformation is also included in the dataset. Different correlation length (CL) and root mean square (RMS) heights values are characterized.
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24 February 2023
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1.0.0
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