Response compaction for system-on-a-chip based on advanced convolutional codes (Q882714)

This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output compactor based on a \((n, n-1, m, 3)\) convolutional code is presented. When the proposed theorems are satisfied, the compactor can avoid two and any odd erroneous bits cancellations, and handle one unknown bit (X bit). When the X bits in response are clustered, multiple-weight check matrix design algorithm can be used to reduce the effect of massive X bits. Some extended experimental results show that the proposed encoder has an acceptable-level X tolerant capacity and low error cancellations probability.