On the performance of transputer arrays for dense linear systems (Q921858)

This paper presents the results of an experimental investigation of the computation and communication performance for single and multitransputer arrays. The study is focussed on the normalized arithmetic, concurrent floating and integer arithmetic, logarithmic array indexing, and on- chip/off-chip RAM; startup time, byte transfer rate, asymptotic link bandwidth, and the effect of the use of some performance maximization techniques on execution time. Also, the half performance message length for simultaneous operation of k \((k=1,...,4)\) links at 10/20 MHz clock in uni- and bidirectional modes is estimated. This study has been made for matrix factorization algorithms for dense linear systems, including LUD, Householder, Gauss-Jordan, Cholesky and Givens methods. The main directions of a future investigation are also presented.