An efficient hardware accelerator architecture for implementing fast IMDCT computation (Q985619)
From MaRDI portal
 | This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use this page instead for the normal view: An efficient hardware accelerator architecture for implementing fast IMDCT computation |
scientific article; zbMATH DE number 5764579
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | An efficient hardware accelerator architecture for implementing fast IMDCT computation |
scientific article; zbMATH DE number 5764579 |
Statements
An efficient hardware accelerator architecture for implementing fast IMDCT computation (English)
0 references
6 August 2010
0 references
hardware accelerators
0 references
inverse modified discrete cosine transform
0 references
type-IV discrete cosine/sine transform
0 references
type-II inverse discrete cosine transform
0 references
