Sudhakar Yalamanchili

Available identifiers

Publication	Date of Publication	Type
Efficiently Solving Partial Differential Equations in a Partially Reconfigurable Specialized Hardware	2022-03-23	Paper
Instruction-throughput regulation in computer processors with data-center applications	2018-04-18	Paper
Performance regulation of event-driven dynamical systems using infinitesimal perturbation analysis	2016-09-09	Paper
Temperature Regulation in Multicore Processors Using Adjustable-Gain Integral Controllers	2015-07-22	Paper
MMR: a multimedia router architecture to support hybrid workloads	2006-05-22	Paper
Advances in Computer Science - ASIAN 2004. Higher-Level Decision Making	2005-08-17	Paper
Distributed, deadlock-free routing in faulty, pipelined, direct interconnection networks	2003-11-02	Paper
Augmented binary hypercube: a new architecture for processor management	2003-10-26	Paper
https://portal.mardi4nfdi.de/entity/Q4417466	2003-07-29	Paper
https://portal.mardi4nfdi.de/entity/Q4417533	2003-07-29	Paper
https://portal.mardi4nfdi.de/entity/Q2777272	2002-03-07	Paper
https://portal.mardi4nfdi.de/entity/Q5688927	1997-06-09	Paper
Parallelism in sequential multiprocessor simulation models	1996-06-13	Paper
A performance model of pipelined k-ary n-cubes	1995-01-01	Paper

No records found.

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MaRDI profile type	MaRDI person profile
instance of	human

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