Linear-size log-depth negation-limited inverter for \(k\)-tonic binary sequences

DOI10.1016/j.tcs.2008.10.030zbMath1171.68014OpenAlexW2174212315MaRDI QIDQ1007246

Jun Tarui, Hiroki Morizumi

Publication date: 20 March 2009

Published in: Theoretical Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.tcs.2008.10.030

zbMATH Keywords

circuit complexitynegation-limited circuit

Mathematics Subject Classification ID

Cites Work

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• On the negation-limited circuit complexity of merging
• Higher lower bounds on monotone size
• On the Inversion Complexity of a System of Functions
• On the Negation-Limited Circuit Complexity of Sorting and Inverting k-tonic Sequences
• On the Complexity of Negation-Limited Boolean Networks
• Negation-Limited Complexity of Parity and Inverters
• A Superpolynomial Lower Bound for a Circuit Computing the Clique Function with at most (1/6)log log n Negation Gates

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